1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit (IC) manufacturing, and, more specifically, to an isolation region that is dense and planar, as well as, a method of forming such an isolation region.
2. Discussion of Related Art
Gordon Moore originally suggested in 1964 that the pace of technology innovation would result in the doubling of the number of transistors per unit area on an IC chip every 12 months. By 1975, the trend had changed to a doubling every 18 months. Over the ensuing decades, the semiconductor industry has adhered closely to Moore's Law in improving density for every generation of devices. Maintaining such a schedule has involved the scaling down of the metal oxide semiconductor field effect transistors (MOSFETs) in complementary metal oxide semiconductor (CMOS) circuits by using shorter gate length, thinner gate dielectric, super-steep retrograde wells, triple wells, abrupt source/drain (S/D) junctions, and highly-doped channels.
However, doping the channel to a concentration higher than 1018/cm3 tends to degrade carrier mobility and junction characteristics. Tunneling of electrons through the gate dielectric also becomes a problem when the gate dielectric thickness drops below about 1.5 nanometers (nm). Consequently, starting with the 90 nm technology node and continuing with the 65 nm technology node, scaling of planar devices fabricated in bulk silicon substrate has become increasingly hampered by short-channel effects (SCE), such as leakage and threshold voltage, Vt, stability.
Thus, even more drastic changes are now required in device structure and manufacturing process in order to address SCE. One significant change is substrate enhancement, such as silicon-on-insulator (SOI) technology, in which a device is built in a thin silicon body located over an embedded layer of oxide. SOI can lower parasitic capacitance and reduce substrate leakage thereby enabling faster switching speeds and lower-voltage operation. Devices built with SOI can maintain a higher drive current, Ion, than devices built in bulk silicon while minimizing off-state leakage current, Ioff. Lowering threshold voltage allows the SOI thickness to be reduced and reducing the SOI thickness allows much better control over SCE. Threshold voltage, Vt, also becomes more constant across different channel lengths below about 0.6 micron (um).
An SOI device is considered to be partially-depleted when the depletion region in the channel below the gate electrode does not extend all the way through the thickness of the silicon body. Unfortunately, the performance gain of partially-depleted SOI devices over standard bulk silicon devices diminishes as the dimensions continue to be scaled down. Partially-depleted SOI devices are also subject to a floating body effect (FBE) which makes circuit design more difficult.
Devices built in SOI change from partially-depleted to fully-depleted when the thickness of the silicon body becomes less than about 40 nm. An SOI device is considered to be fully-depleted when the depletion region extends all the way through the thickness of the silicon body. Fully-depleted SOI devices allow a smaller gate size and more ideal transistor function with very sharp turn-on characteristics.
A mesa isolation process may be used for fully-depleted SOI devices, but such a process is not very planar.
Thus, what is needed is an isolation region that is dense and planar, as well as a method of forming such an isolation region.